In fabricating semiconductor devices or, in particular, analog devices, capacitors must be formed in most cases and a contact hole has to be formed to connect a lower metal layer to another metal line. Generally, the contact hole is formed before or after the formation of the capacitor.
FIGS. 1a and 1b illustrate, in cross-sectional views, a known process for forming a capacitor of a semiconductor device. Referring to FIG. 1a, a metal such as copper or aluminum is deposited on a substrate (not shown) to form a metal line 1′. A titanium nitride (TiN) layer 2′ is deposited on the metal line 1′. The TiN layer 2′ is used as a lower metal layer of a capacitor. An insulating layer 3′ such as oxide or nitride is formed on the TiN layer 2′ and an upper metal layer 4′ is formed on the insulating layer 3′. Then, a mask layer such as a photoresist pattern 5′ is formed on the upper metal layer 4′. Next, some parts of the upper metal layer 4′, the insulating layer 3′, and the TiN layer 2′ are removed by wet or dry etching using the photoresist pattern as a mask. As a result, as shown in FIG. 1b, a capacitor comprising the upper metal layer 4′, the insulating layer 3′, and the TiN layer 2′ is formed on the metal line 1′.
For example, U.S. Pat. No. 6,117,747 to Shao et al. discloses a method for fabricating a metal-oxide capacitor using a dual damascene process. U.S. Pat. No. 6,387,775 to Jang et al. discloses a method for forming a metal-insulator-metal (MIM) capacitor while preserving the dielectric capacitor during the trench etch. As another example, U.S. Pat. No. 6,329,234 to Ma et al. discloses a structure and a method for fabricating copper metal-insulator-metal (MIM) capacitors and thick metal inductors simultaneously with only one mask in a damascene and dual damascene trench/via process. High performance device structures formed by Ma et el. patent include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, MIM capacitors, thick inductor metal wiring, interconnects and contact vias.
However, if a capacitor and a contact hole are formed separately, the process for manufacturing a semiconductor device become unnecessarily longer and more complicated and probability of defect occurrence increases. In addition, in an etching process, it is difficult to accurately adjust depth and location of etch-stop and conduct process control because both a lower metal layer and a metal line are formed of metals and an etch selectivity of the lower metal layer to the metal line is low.